The present invention relates to semiconductor memory devices, such as random access memories, and more particularly to a single intersection type (open bit line type) semiconductor memory device in which bit lines connected to dynamic memory cells extends to the left and right of a sense amplifier column placed at the center.
Japanese Unexamined Patent Publication Nos. 59-2365 and 2001-118999 are examples of conventional semiconductor memory devices. The techniques disclosed in these publications pertain to a single intersection type (open bit line type) dynamic RAM that comprises dynamic memory cells each having a transistor and a capacitor, word lines, and bit lines, and that two bit lines constituting a complimentary bit line pair extend to the left and right of a sense amplifier column placed at the center.
The first one of the publications aims at avoiding that, in the case of using an information-storing capacitor utilizing a MOS capacitor, fluctuation of power supply voltage due to the operations of peripheral circuits is not transmitted to the entire two plate electrodes that are separately placed to the left and right of the sense amplifier column. For this purpose, first wiring line connected to respective plate electrodes at a plurality of locations are disposed along the direction perpendicular to bit lines, and the first wiring lines connected to respective plate electrodes are connected to each other by a second wiring line, the central portion of which is connected to a power supply line of a peripheral circuit by a third wiring line. With this configuration, the potentials of the plate electrodes are maintained uniform as a whole even when the potentials of peripheral circuits fluctuate.
On the other hand, the second one of the publications shows that, in cases where the information-storing capacitor is of COB (capacitor over bit line) type or one of the electrodes of the information storing capacitor has a cylindrical shape formed on the inner wall of a hole in the interlayer insulating film, common plate electrodes of the capacitors of a plurality of dynamic memory cells arranged to both the left and right sides of the sense amplifier column placed at the center are connected to each other, in order to reduce plate noise caused by parasitic capacitance between bit lines and the plate electrodes.
In recent years, commercialization of DRAM merged LSIs in which logic circuits and dynamic RAM are incorporated in a single chip has been actively sought. The memory capacity of the dynamic RAM that is incorporated in the DRAM merged LSI is relatively smaller than those of general-purpose DRAMs, and they are required to have a similar degree of transistor performance and cost reduction to standard CMOSs. In view of this, it is effective to incorporate a dynamic RAM using planar memory cells, which can be manufactured by a standard CMOS process. In addition, it is desired that the operational system be a single intersection type (open bit line type) to reduce the size of the dynamic RAM.
However, as the present inventors studied the noise interference in single intersection type dynamic RAMs, it has been found that interference noise between adjacent bit lines is dominant among the noise interference concerning recent microfabrication processes and that there is noise that is not negligible on the plate electrodes. To reduce the plate noise, it is insufficient to stabilize plate potentials using the techniques disclosed in the foregoing first and second publications. Moreover, no suggestions are made for the interference noise between adjacent bit lines. Furthermore, both techniques in the publications require an additional step of forming the plate electrodes in addition to the step of forming the gate electrodes of transistors, and therefore, they have drawbacks of many fabrication steps and increased wafer cost.
With reference to FIGS. 15 and 16, deterioration of operational margin of memory arrays caused by interference between adjacent bit lines is discussed below.
As shown in FIG. 15, in a single intersection type memory array in which memory arrays MATA and MATB are respectively disposed on the left and right of a sense amplifier column, parasitic capacitance exists between adjacent bit lines. As an example, the following describes a case where a word line WL0A of the memory array MATA is selected to read out data from memory cells MC and a high level is read out from a bit line BL1 whereas a low level is read out from other bit lines BL0 and BL2 to BLn.
In this case, since the data of the bit lines BL0 and BL2 that are adjacent to the bit line BL1 are inverted data, the bit line BL1 receives coupling noise via parasitic capacitances Cbs01A and Cbs12A between the adjacent bit lines, and as a result, the read potential that appears in this bit line BL1 is small. One the other hand, the potentials of bit lines NBL0 to NBLn that are at the memory array MATB side, which are reference potentials, do not fluctuate. Accordingly, concerning the potential difference between the complementary bit line pair at the time when amplifying operation is started by the sense amplifier, the read potential difference in the complementary bit line pair (BL1, NBL1) is smaller than those of other complementary bit line pairs. When amplifying operation is performed by the sense amplifier under this state, it is often the case that data are erroneously amplified if the sense amplifier is off-balance because the read margin for the high level is small in the bit line BL1.
In addition, when an amplifying operation is performed under the state in which the high level signal of the bit line BL1 is small and the low level signals of the other bit lines BL0 and BL2 to BLn are large, the amplifying speed of the bit lines BL0 and BL2 to BLn is fast but the amplifying speed of the bit line BL1 is slow. In this case as well, negative phase noise occurs in the bit line BL1 via the parasitic capacitances Cbs01A and Cbs12A between the bit lines, and negative phase noise occurs also in the bit line NBL1 at the memory array MATB side via parasitic capacitances Cbs01B and Cbs12B. Because these noises further delay the amplifying speed of the complementary bit line pair (BL1, NBL1), the data of the complementary bit line pair (BL1, NBL1) are inverted, resulting in a read error.
Thus, in single intersection type memory arrays, there is a possibility of read errors depending on data patterns read out to the bit lines because parasitic capacitance exists between adjacent bit lines. In particular, when the amount of signal charge stored in a memory cell reduces due to leak current or the like, the signal level read out to the bit line further reduces, further increasing the possibility of read errors.
Further, conventional dynamic RAMs have the following drawbacks. If they have large sense amplifier circuits, the degree of integration is small. In addition, if they have large operational variations between N-channel and P-channel pair transistors constituting the sense amplifier circuits, their operations are not stable and there is a possibility of data read errors.